1. Field of the Invention
The present invention relates to a data transmission system controller, and more particularly, to a method and apparatus for preventing memory overrun in a data transmission system using a High Level Data Link Control (HDLC) protocol.
2. Description of the Prior Art
The HDLC protocol is Data Link (Layer 2) protocol for establishing a reliable communication link between a source and a destination. The HDLC protocol is based on a sliding window protocol and uses different data frames to handle connection, termination, and exchange of user data and link control. HDLC frames each include an address that must be processed independently of the addresses for other HDLC frames. HDLC controllers, receive, parse, interpret, and respond to messages transmitted in the HDLC format. The HDLC controller, together with a central processing unit and a shared memory, format and de-format the flag, bit stuff, and checksum bits for the HDLC frames.
One type of HDLC controller is the MUNICH32 manufactured by Siemens(copyright) corporation. The MUNICH32 can handle up to 32 1.536/1.544 Mbits/second T1/DS1 channels, 32 2.048 Mbits/second CEPT channels, or 4.096 Mbits/second 32-channel Pulse Code Modulation (PCM) bus. The PCM bus is the actual physical media used to transport digital signals, e.g., DS1, DS2, DS3, etc. The HDLC controller processes HDLC frames at bit rates from 8 Kbits/second up to 2.048 Mbits/second. A 64-channel Direct Memory. Access (DMA) controller exchanges data and channel control information between the MUNICH32 and the shared memory. The MUNICH32 and other types of HDLC controllers are well known to those skilled in the art and are therefore not explained in further detail.
A block diagram of a data transmission system 10 is shown in FIG. 1. The data transmission system 10 includes an HDLC controller 12, a central processing unit (CPU) 18, and a memory 20. The HDLC controller 12 transfers HDLC frames between a PCM bus 24 and the memory 20 using a 32-bit system bus 22. The memory 20 is a Random Access Memory (RAM) shared between the HDLC controller 12 and the CPU 18 through the system bus 22. The HDLC controller 12 includes a receive buffer 14. The receive buffer 14 is a 256-byte first-in-first-out (FIFO) buffer that can buffer 8 complete HDLC frames before transferring the buffered data into the shared memory 20. Although a single HDLC controller 12 is shown in FIG. 1, each time slot can be shared between up to four HDLC controllers using sub-channeling. Thus, four controllers can handle four different D-channels in one single time slot.
The CPU 18 and the HDLC controller 12 communicate with each other primarily through the shared memory 20. At start up, the CPU 18 initializes the controller 12 by creating a valid data buffer 42. (shown in FIGS. 3A-4E) and writing configuration information required by the HDLC controller 12 into the shared memory 20. The HDLC controller 12 reads the configuration information from the shared memory 20 and transfers data stored in the receive buffer 14 to the valid buffer 42.
The division of shared memory 20 for the MUNICH32 HDLC controller 12 is shown in FIG. 2. The HDLC controller 12 requires that the shared memory 20 include a programmable configuration start address 30, a control and configuration section (CCS) 32, and a variable size interrupt circular queue 34. The HDLC controller 12 also includes receive descriptors 36, receive data section 37, transmit descriptors 38, and transmit data section 39 for each channel. The shared memory 20 allocated for each transmit and receive channel is organized as a chained list of buffers 42. Each chained list of buffers 42 is composed of the receive and transmit descriptors 36 and 38, respectively, and the receive and transmit data sections 37 and 39, respectively. The receive descriptors 36 and the transmit descriptors 38 each contain a pointer to the next descriptor, a start address, and an address to a corresponding data section 37 or 39. The descriptors 36 and 38 also include control information, e.g., a frame end indication, transmission hold, and rate adaption with interface time fill.
Since the HDLC controller 12 (FIG. 1) has no internal programmable or pollable registers, commands from the CPU 18 are transmitted to the HDLC controller 12 by updating the CCS section 32 of the memory 20. The CPU 18 then issues an Action Request (AR) instruction to the HDLC controller 12. The controller 12 responds back with an Action Acknowledge (ARACK) instruction or a Failure-To-Do-The-Operation (ARF) instruction. HDLC controllers 12, like the MUNICH32 controller, prohibit an AR instruction during the time a preceding instruction has not been acknowledged by an ARACK or an ARF instruction or when a pulse signal is present at the RESET pin (not shown).
In order to stop the HDLC controller 12 from receiving data from the PCM bus 24, the CPU 18 sends a first set of instructions to the controller 12. This first set of instructions includes a Receive Abort (RA) instruction followed by a Receive Off (RO) instruction. The HDLC controller 12 responds back to the CPU 18 with an ARACK or an ARF for each of the instructions, indicating that the HDLC controller 12 is no longer receiving data from the PCM bus 24. A problem with HDLC controllers 12 such as the MUNICH32 controller is that even though data reception at the controller 12 is terminated, the transfer of data from the receive buffer 14 to buffers 42 in memory 20 continues. Thus, the HDLC controller 12 may inadvertently write over or corrupt pre-existing data or unprocessed data in buffers 42.
FIGS. 3A-3C are block diagrams showing the memory overrun problem in the data transmission system 10. In FIG. 3A, the CPU 18 first sends an RA instruction followed by an RO instruction to the HDLC controller 12 for terminating data reception. Under normal operating conditions in FIG. 3B, the HDLC controller 12 responds with an ARACK instruction for each sent RA and RO instruction. At this point, the HDLC controller 12 in FIG. 3C no longer receives data from the PCM bus 24. Although no longer receiving data, the HDLC controller 12 continues to transfer the data contained in its receive buffer 14 to the buffer 42 in shared memory 20. The buffer 42 may contain data 44 that might be overwritten as the HDLC controller 12 continues to transfer data from receive buffer 14 to buffer 42. After the CPU 18 receives acknowledgement of data termination from the controller 12, i.e., an ARACK or ARF instruction, the CPU 18 terminates buffer 42, releasing the memory space for use by another controller 12 or subsystem (not shown). Thus, the HDLC controller 12 may inadvertently write over valid data in a newly created buffer used by another controller 12 or subsystem or may write past the end of the buffer 42 in memory 20 with the data in receive buffer 14.
Accordingly, a need remains for a method and apparatus for preventing memory overrun or corruption in a data transmission system controllers.
The present invention concerns a method and apparatus for preventing memory overrun in a data transmission system. The data transmission system includes a CPU, an HDLC controller having a receive buffer, and a memory shared between the CPU and the HDLC controller. A particular embodiment of the invention includes descriptor registers created in the shared memory by the CPU for use by the HDLC controller. A data reception termination instruction is sent from the processor to the HDLC controller to terminate data reception by the HDLC controller from the PCM bus. The HDLC controller generates and sends an acknowledgement instruction to the processor responsive to the data reception termination instruction.
Thereafter, the CPU creates an empty memory buffer in the shared memory responsive to receiving the acknowledgement instruction and makes the descriptor registers in the shared memory point to the empty memory buffer. By doing so, data transfers from the HDLC controller 12 to the memory 20 occurring after the processor has terminated data reception are written into the empty memory. Since the empty memory buffer does not contain valid data, the HDLC controller cannot overwrite or corrupt existing data by appending onto an existing data buffer or by writing over a descriptor that might contain unprocessed data.